1. Field of the Invention
This invention relates generally to a defect classification methodology in a semiconductor manufacturing testing system and more specifically, to an automatic defect classification methodology that determines if a defect is a propagator and utilizes a feedback mechanism to search and amend the historical database of the defect in question.
2. Discussion of the Related Art
In order to remain competitive, a semiconductor manufacturer must continuously increase the performance of the semiconductor integrated circuits being manufactured and at the same time, reduce the cost of the semiconductor integrated circuits. Part of the increase in performance and the reduction in cost of the semiconductor integrated circuits is accomplished by shrinking the device dimensions and by increasing the number of circuits per unit area on an integrated circuit chip. Another part of reducing the cost of a semiconductor chip is to increase the yield. As is known in the semiconductor manufacturing art, the yield of chips (also known as die) from each wafer is not 100% because of defects during the manufacturing process. The number of good chips obtained from a wafer determines the yield. As can be appreciated, chips that must be discarded because of a defect or defects increases the cost of the remaining usable chips.
A single semiconductor chip can require numerous process steps such as oxidation, etching, metallization and wet chemical cleaning. Some of these process steps involve placing the wafer on which the semiconductor chips are being manufactured into different tools during the manufacturing process. The optimization of each of these process steps requires an understanding of a variety of chemical reactions and physical processes in order to produce high performance, high yield circuits. The ability to view and characterize the surface and interface layers of a semiconductor chip in terms of their morphology, chemical composition and distribution is an invaluable aid to those involved in research and development, process, problem solving, and failure analysis of integrated circuits.
Although it would be desirable to be able to identify and analyze each defect on each wafer in every manufacturing run it is not practical. In practice, a particular lot (a number of wafers) is selected to be representative of the manufacturing run. A single wafer or multiple wafers can be selected from the lot to be analyzed. Because of the number of processes, it may not be possible to re-analyze each wafer after each process. Therefore, only certain processes may be selected to be analyzed. After each process that has been selected to be analyzed, the wafer is placed in an inspection tool that identifies defects. As can be appreciated, there may be more defects than can be practically analyzed.
In the field of in-line defect capture and analysis there is a tri-pronged focus of effort to try to explain the past (what has happened to the wafer), the present (what is happening to the wafer), and the future (what will happen to the wafer). Because of the number of defects that must be analyzed or accounted for, techniques have been developed to assist in the practical analysis of defects. One technique is called partitioning. Partitioning is a technique in which defects from the current layer of the wafer are mapped against defects from previous layers of the same wafer and any defect from the current layer found within a certain radius of any previous layer defect is marked as a previous layer defect. The rational for this is that the defects within a certain radius are probably the same defect. Because of this probability, only one of the previous layer defects within the selected radius is selected to be analyzed because to analyze further defects within the selected radius would be a waste of resources, that is, testing time and effort. The technique of partitioning separates previous layer defects from current layer defects, which are called "adders" and which are therefore eligible to be selected to be analyzed with the other defects in the current layer. Another technique to assist in the analysis of defects is declustering, which is a method by which all defects within a certain radius of each other are treated as a single defect, since it is probable that they were caused by the same event, such as a scratch, patch of residue, etc.
Presently, there is no method by which a detected defect in the present layer can be identified as a propagator and further, if it is a propagator, whether it will be a killer (die destructive) defect. Without such a method, a defect that may be a killer defect may be considered to be a benign defect. The early and proper classification of possible killer defect information is critical for any models or simulators, which will subsequently use this data for predicting or forecasting yields. In addition, it will place knowledge relating to the potential destructive nature of the defect in the hands of the process engineer so an intelligent decision can be made whether to scrap or send on wafers when dispositioning lots.
Therefore, what is needed is a method to determine whether a defect is a propagator and a method to update the defect data for those defects determined to be a propagator.